The present invention relates to an electronic circuit for communicating in trinary logic. More particularly, the invention involves, in its various facets, configurations of electronic devices suitable to receive a trinary level signal on a single input and provide a noise and transition "glitch" insensitive binary state output, or a fully decoded output on three lines.
The use of trinary logic for electronic circuits is relatively well-known. For example, U.S. Pat. Nos. 4,202,044 and 4,488,065 relate to the storage and retrieval of memory array data stored in trinary format. U.S Pat. No. 4,449,065 involves a circuit for converting a single trinary input signal into a pair of binary output signals using a clocked precharging. U.S. Pat. No. 3,832,576 introduces various circuit techniques for decoding a pair of binary outputs with logic gates. Although similar concepts exist in these representative prior teachings, the implementations are relatively constrained to particular circuit embodiments and provide no specific feedback compensation to offset for either input signal noise effects or slow input signal transition induced output state glitches.